1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit fabrication. More particularly, the present invention relates to a process of planarizing crown capacitors for integrated circuitry.
2. Description of the Related Art
The crown capacitor has been widely applied to the dynamic random access memory (DRAM), for providing sufficient capacitance as semiconductor devices scale down in size. In the conventional process of manufacturing the crown capacitor, the bottom electrode is configured with an inner sidewall and outer sidewall to be exposed, thus raising a planarization issue. To overcome this problem, one approach is to apply an additional chemical mechanical polishing (CMP) process after the inner sidewall and the outer sidewall of the bottom electrode has been exposed; the other approach makes use of a photoresist layer, formed through an extra photolithography process, to overlie the peripheral circuit area while insulating material is filled onto the exposed inner sidewall and outer sidewall in the cell area.